Interconnect structure and method in programmable devices

ABSTRACT

An improved interconnect structure in programmable devices gives a new dimension to the routing architecture, where architecture is divided into various domains. It includes at least one set of input lines, each said set having predetermined number of input lines; an equal number of sets of routing lines, each said set of routing lines being connected to a corresponding set of input lines using a switch box; thereby forming domain based routing structures, each domain being disjoint with the other domain. Segregating FPGA routing resources into various independent routing domains is done; each domain providing connectivity to route a signal to a set of sinks.

PRIORITY CLAIM

This application claims priority from Indian patent application No.2114/Del/2004, filed Oct. 27, 2004, which is incorporated herein byreference.

FIELD OF THE INVENTION

The present invention pertains to an improved interconnect structure inprogrammable devices.

BACKGROUND OF THE INVENTION

When Integrated Circuits (ICs) were first introduced, they wereextremely expensive and were limited in their functionality. Rapidstrides in semiconductor technology have vastly reduced the cost whilesimultaneously increasing the performance of IC chips. However, thedesign, layout, and fabrication process for a dedicated, custom built ICremains quite costly. This is especially true for those instances whereonly a small quantity of a custom designed IC is to be manufactured.Moreover, the turn-around time (i.e., the time from initial design to afinished product) can frequently be quite lengthy, especially forcomplex circuit designs. For electronic and computer products, it iscritical to be the first to market. Furthermore, for custom ICs, it israther difficult to effect changes to the initial design. It takes time,effort, and money to make any necessary changes.

In view of the shortcomings associated with custom IC's, fieldprogrammable gate arrays (FPGAs) offer an attractive solution in manyinstances. Basically, FPGAs are standard, high-density, off-the-shelfICs, which can be programmed by the user to a desired configuration.Circuit designers first define the desired logic functions, and the FPGAis programmed to process the input signals accordingly. Thereby, FPGAimplementations can be designed, verified, and revised in a quick andefficient manner. Depending on the logic density requirements andproduction volumes, FPGAs are superior alternatives in terms of cost andtime-to-market.

An FPGA essentially consists of an outer ring of I/O blocks surroundingan interior matrix of configurable logic blocks. The I/O blocks residingon the periphery of an FPGA are user programmable, such that each blockcan be programmed independently to be an input or an output and can alsobe tri-stated. Each logic block typically contains programmablecombinatorial logic and storage registers. The combinatorial logic isused to perform Boolean functions on its input variables. Often, theregisters are loaded directly from a logic block input, or they can beloaded from the combinatorial logic.

Interconnect resources occupy the channels between the rows and columnsof the matrix of logic blocks and also between the logic blocks and theI/O blocks. These interconnect resources provide the flexibility tocontrol the interconnection between two designated points on the chip.Usually, a metal network of lines runs horizontally and vertically inthe rows and columns between the logic blocks. Programmable switchesconnect the inputs and outputs of the logic blocks and I/O blocks tothese metal lines (called input & output connection boxes). Crosspointswitches and interchanges at the intersections of rows and columns areused to switch signals from one line to another (called switch boxes).Often, long lines are used to run the entire length and/or breadth ofthe chip.

The functions of the I/O blocks, logic blocks, and their respectiveinterconnections are all programmable. Typically, a configurationprogram stored in an on-chip memory controls these functions. Theconfiguration program is loaded automatically from an external memoryupon power-up, on command, or programmed by a microprocessor as part ofsystem initialization.

A typical symmetrical FPGA architecture is shown in the FIG. 1. Figureshows basic components and their connectivity. FIG. 1 shows a switch boxand 4 connection boxes of logic block connecting to a bi-directionalsingle length track routing fabric. The four connection boxes areidentical. The Configurable logic block has its inputs connected to therouting fabric via a matrix, usually known as a connection box. Routingchannels interact with each other with a matrix, known as a switch box.The switch box can be of different topologies. Recently much work hasbeen concentrated on a superior switch box called Hyper Universal, whichprovides enhanced routability at the expense of some extra resources.

With further developments taking place, the connection boxes of a logiccluster shown in FIG. 1 are not in the four adjacent channels but are onall four sides of a particular switch box making the connection box andswitch box appear as one single entity as shown in FIG. 2.

The disjoint switch box is very popular because of its simplicity andeasy layoutability. A disjoint switch box is shown in FIG. 3. A disjointswitch box has similar one to one connection on all the sides, i.e.,line number 1 of side left is connected to line number of 1 of right,top and bottom and so on. Such a switch box makes it easier for a routerto predict the routability and because of of fewer number of crisscrossconnections it is easy to layout in silicon. However a disjoint switchbox gives a reduced routability as compared to other switch boxes likeWilton, Universal & Hyper-Universal.

A typical configurable logic block would be as shown in FIG. 4. Thelogic block shown has a full matrix on the input side of itsconnectivity with the routing fabric, known as INMUX and internalfeedback matrix for merged nets. It could also possibly have a fullmatrix on the output side to connect to the routing fabric. Generic FPGAstructures are referred to in M. I. Masud. FPGA routing structures: Anovel switch block and depopulated interconnect matrix architectures.Master's thesis, Department of Electrical and Computer Engineering,University of British Columbia, December 1999.

Another structure is given in G. Lemieux, P. Leventis, and D. Lewis.Generating highly-routable sparse crossbars for PLDs. In ACM/SIGDA Int.Symp. on FPGAs, pages 155-164, Monterey, Calif., February 2000.

But unlike universal switch-boxes, disjoint switch boxes are better withrespect to predicting routing and are easy to layout on silicon.

SUMMARY OF THE INVENTION

To obviate the above drawbacks, an aspect of the invention provides fora domain based routing architecture where routing architecture isdivided into various domains.

Another aspect provides easy routing predictability and improved routingflexibility as well as improved compile times for EDA tools.

According to one aspect of the present invention, an improvedinterconnect structure in programmable devices includes one or moreindependent groups of input lines, each said group having predeterminednumber of said input lines; an equal number of groups of routing lines;and a connection mechanism for connecting lines in each input group tothe lines in each corresponding group of routing lines and lines of eachgroup of routing lines with the routing lines of same group, therebyforming domain based routing structures, each said domain being disjointwith the other domain.

The output lines of a logic block may be connected to any group ofrouting lines. The group of routing lines may contain a plurality ofrouting lines. The connection mechanism may include switch box (s) andconnection boxes. Each group of input lines can drive a domain usingconnection boxes. The one or more independent groups of input lines candrive at least one domain using the routing lines. Each domain mayinclude a switch box. All domains may include a common switch box. Thegroup of input lines may be connected to the address/data lines of amemory in programmable devices. The routing lines may beunidirectional/bi-directional. The switch box may include disjointswitch boxes. The switch box may include universal switch boxes. Theswitch box may include Wilton switch boxes. The switch box may includehyper universal switch boxes. The programmable device may include anFPGA.

According to another aspect of the present invention a method forinterconnecting programmable devices includes the steps of forming atleast one independent group of input lines, each group having apredefined number of said input lines; providing equal number of groupsof routing lines, each group comprising plurality of routing lines; andconnecting each said group of input lines to a corresponding group ofrouting lines and lines of each group of routing lines with the routinglines of same group thereby forming a domain based routing structureenhancing software implementation as well as layouts. The group of inputlines may be formed depending upon logical equivalence or functionalityof input lines.

BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS

The invention will now be described with reference to the accompanyingdrawings.

FIG. 1 shows a symmetrical FPGA architecture with basic components.

FIG. 2 shows a symmetrical architecture with different connectivity.

FIG. 3 shows a simple Disjoint Switch Box topology.

FIG. 4 shows a generic logic cluster with in multiplexer and input sets.

FIG. 5 shows a routing fabric broken in four routing domains in switchbox, connection box and in multiplexer for bi-directional routing tracksusing a single switch box.

FIG. 6 illustrates a routing fabric broken into four routing domains inwhole core.

FIG. 7 illustrates a routing fabric broken in four routing domains inswitch box, connection box and IN MUX for uni-directional routingtracks.

FIG. 8 re-layout of FIG. 5 using multiple switch boxes.

FIG. 9 shows a universal switch boxes doing intra domain switching witha routing fabric broken into four domains.

DETAILED DESCRIPTION OF THE INVENTION

The following discussion is presented to enable a person skilled in theart to make and use the invention. Various modifications to theembodiments will be readily apparent to those skilled in the art, andthe generic principles herein may be applied to other embodiments andapplications without departing from the spirit and scope of the presentinvention. Thus, the present invention is not intended to be limited tothe embodiments shown, but is to be accorded the widest scope consistentwith the principles and features disclosed herein.

Embodiments of the invention combine the features of a disjointswitch-box and various other switch-boxes to give a balanced tradeoff ofroutability, easy layoutability & software friendliness. Theshortcomings of disjoint switch box have been overcome by a combinationof disjoint and other type of switch boxes to yield a switch-box clusterwith ease of layoutability, software friendly structure & increasedroutability.

Referring to FIG. 4, the IN MUX 40 input is segregated into various sets(A, B, C & D) based on different criteria, such as logical equivalenceor functionality. If IN MUX 40 is a full matrix then all inputs of INMUX 40 are logically equivalent, i.e., there is just one set of inputsat INMUX 40. If there is no IN MUX then different look-up-table (LUT)inputs may form different sets (say a first set for LUT 41 input, asecond set for LUT 42 inputs and so on). If there is memory in place ofa LUT then address lines may form one set, data line may form anotherset and so on.

The domains may not necessarily be created by the connectivity to inputmatrices but could also be possible in other cases. For example, directconnectivity to the cluster of LUTs can lead to domain formation on thebases of connectivity to a particular LUT, i.e., tracks connected to aparticular LUT are of the same domain. In memories, domains can beformed on different criteria, e.g., there could be one domain of datalines, another domain of address lines, yet another domain of controlsignals and the like.

However in FIG. 4, IN MUX 40 inputs have been segregated into four sets,say A, B, C and D, using any aforesaid method.

FIG. 5 shows a detailed view of a logic tile. Logic tile contains alogic block 50 (IN MUX is part of the logic block), connection box 51and switch box 52. All the lines (inputs) of the logic block are dividedinto four sets A, B, C and D. The inputs are connected to the routinglines, which are again divided into different sets and interact withtheir corresponding lines on all sides of a switch box thereby forming adomain.

Connection box 51 is designed in such a way that different sets interactwith different logic block input sets. In FIG. 4, tracks on each sideare divided into four parts and one fourth lines (1 to 4) of each sideare connected to set A, another one fourth lines (5 to 8) of each sideare connected to set B, another one fourth lines (9 to 12) of each sideare connected to set C and remaining one fourth lines (13 to 16) of eachside are connected to set D. The routing tracks are divided into fourparts as shown, however, they can be divided into any number of sets,usually equal to the number of sets in logic block 50 inputs and eachrouting track interacts with one input line, but flexibility at theconnection box 5 can be changed to any value provided first one fourthof the lines are being connected to set A and so on. FIG. 4 shows onepossible method of connecting routing lines to respective sets of inputlines on the logic block 50 whereas there may be various other possiblemethods that can be deployed to achieve the same goal.

The switch box 52 is disjoint in nature, i.e., line number 1 of left isalways connected to line number 1 of top, bottom and right and so on foreach line and side.

The connection between the lines of input multiplexer, say set A, androuting lines is as follows. The required number of routing lines of thefirst side are connected to set A of the connection box 51 which, inturn, are connected to the corresponding lines on all other sides of aswitch box 52. Thus, all these lines are connected to set A inconnection box. In brief, line number 1 will always remain connected toset A on all sides even after passing through switch box and connectionbox. All lines interacting with set A belong to domain 1, all linesinteracting with set B belong to domain 2, all lines interacting withset C belong to domain 3 and all lines interacting with set D belong todomain 4.

FIG. 6 shows a whole chip formed by replication of tiles described inFIG. 5 thereby extending domains to whole FPGA fabric.

The combination of “set definition at logic block”, “connection boxtopology” and “switch box topology” forms routing domains and dividesthe complete routing structure into various domains, which are mutuallyexclusive.

The biggest benefit of routing domains is achieved during softwareimplementation and silicon implementations. Routing domains have muchless connectivity (none in this case as all routing domains are mutuallyexclusive) with each other, hence logic related to a particular domaincan be placed at one place while logic related to another domain can beplaced at another place. It gives a high degree of flexibility duringsilicon routing or “floorplanning.” Different domains can be placedseparately keeping different silicon issues into consideration andthereby provide better performance of silicon in terms of delay and/orarea and/or development efforts.

Also, an FPGA implementation toolset can utilize this feature to improveperformance. During routing, software routes nets between source andsink as per track availability of the routing tracks. The sink isavailable on a particular routing domain (usually just one), which isvalid throughout the chip on all sides; the source need not search thetrack availability on other domains. Rather the source needs to searchthe track availability in a particular domain, which belongs to sink.Thus, domain based routing architecture reduces search space forsoftware considerably.

FIG. 7 is an example of a domain based routing structure in the case ofunidirectional lines. In unidirectional switch box, an incoming line ofa domain in one side drives the corresponding outgoing line an all othersides and so on for each side and incoming/outgoing lines. So a domaincontains logic block input sets and incoming & outgoing lines withappropriate switch box and connection topology.

FIG. 8 shows another embodiment that shows the routing lines have beendivided into domains and the whole switch box is a cluster of disjointswitch boxes. Each switch box is connected to a particular set ofrouting lines/tracks. The segregation of tracks into four domains isbased on their connectivity to the input matrices and switch matrixconnectivity. In this embodiment, neither intra-domain nor inter-domainswitching is possible with respect to tracks. To increase theroutability of such switch boxes while maintaining the domain conceptthe architecture can be depicted as shown in FIG. 9 using universalswitch box.

To enhance routability, other switch boxes like Wilton, Universal &Hyper-Universal can be used in place of a disjoint switch box. Anotherembodiment of invention makes a tradeoff between Disjoint and other highroutability switch boxes to get the best of both types of switch boxes.

In FIG. 9 the switch box is a cluster of mutually exclusive universalswitch boxes. Universal switch boxes give flexibility in layout as theswitch box can be broken in mutually exclusive parts and placed apart asper convenience, as described earlier. The router knows for sure that asignal in one domain is restricted to the domain. So predictability isbetter. This in turn helps to reduce expansion times as well as provideshigh routability (switching tracks is possible in a domain).

Said figure is only an example of a possible structure of a “Clusteredswitch box” which preserves the domain concept. Instead of a universalswitch box a Wilton, Hyper-Universal or a combination of such switchboxes or a new switch box can be used.

Embodiments of the invention can be applied to a routing fabric forFPGAs based on LUTs, multiplexers, ULMs, or CPLDs etc., or memoryelements. Anyone skilled in the art can easily see its applicability toafore mentioned architectures.

FPGAs or other programmable devices including embodiments of the presentinvention may be contained in a variety of different types of electronicsystems, such as computer systems.

From the foregoing it will be appreciated that, although specificembodiments of the invention have been described herein for purposes ofillustration, various modifications may be made without deviating fromthe spirit and scope of the invention.

1. An improved interconnect structure in programmable devicescomprising: one or more independent groups of input lines, each saidgroup having predetermined number of said input lines; an equal numberof groups of routing lines; and a connection mechanism for connectinglines in each input group to the lines in each corresponding group ofrouting lines and lines of each group of routing lines with the routinglines of same group, thereby forming domain based routing structures,each said domain being disjoint with the other domain.
 2. An improvedinterconnect structure as claimed in claim 1 wherein the output lines ofa logic block are connected to any said group of routing lines.
 3. Animproved interconnect structure as claimed in claim 1 wherein said groupof routing lines contains plurality of routing lines.
 4. An improvedinterconnect structure as claimed in claim 1 wherein said connectionmechanism includes switch box (s) and connection boxes.
 5. An improvedinterconnect structure as claimed in claim 1 wherein each said group ofinput lines drives a domain using connection boxes.
 6. An improvedinterconnect structure as claimed in claim 1 wherein said one or moreindependent groups of input lines drive at least one domain using saidrouting lines.
 7. An improved interconnect structure as claimed in claim1 wherein each said domain includes a switch box.
 8. An improvedinterconnect structure as claimed in claim 1 wherein all domains includea common switch box.
 9. An improved interconnect structure as claimed inclaim 1 wherein said group of input lines is connected to theaddress/data lines of a memory in programmable devices.
 10. An improvedinterconnect structure as claimed in claim 3 wherein said routing linesare unidirectional/bi-directional.
 11. An improved interconnectstructure as claimed in claim 7 wherein said switch box includesdisjoint switch boxes.
 12. An improved interconnect structure as claimedin claim 7 wherein said switch box includes universal switch boxes. 13.An improved interconnect structure as claimed in claim 7 wherein saidswitch box includes Wilton switch boxes.
 14. An improved interconnectstructure as claimed in claim 7 wherein said switch box includes hyperuniversal switch boxes.
 15. An improved interconnect structure asclaimed in claim 1 wherein said programmable device includes FPGA.
 16. Amethod for interconnecting programmable devices comprising the steps of:forming atleast one independent group of input lines, each group havinga predefined number of said input lines; providing equal number ofgroups of routing lines, each group comprising plurality of routinglines; connecting each said group of input lines to a correspondinggroup of routing lines and lines of each group of routing lines with therouting lines of same group thereby forming a domain based routingstructure enhancing software implementation as well as layouts.
 17. Themethod for interconnecting programmable devices as claimed in claim 16wherein said group of input lines is formed depending upon logicalequivalence or functionality of said input lines.
 18. An interconnectstructure for a programmable device, the interconnect structurecomprising a plurality of domains, each domain including at least onegroup of input lines and at least one group of routing lines, with therebeing one group of routing lines for each group of input lines and therebeing a number of sets of routing lines, the structure operable toconnect lines in each group of input lines to the routing lines in acorresponding set of routing lines, and to connect the routing lines ineach set of routing lines with the routing lines contained in other setsof routing lines within the same group, and wherein the lines of eachdomain are disjoint relative to the lines of the other domains.
 19. Theinterconnect structure of claim 18 wherein the programmable devicecomprises an FPGA.
 20. The interconnect structure of claim 18 furthercomprising switch boxes for interconnecting sets of routing lines andconnection boxes for interconnecting routing lines and input lines. 21.The interconnect structure of claim 18 wherein each group of input linesincludes a predetermined number of input lines.
 22. An electronicsystem, comprising: an electronic subsystem including a programmabledevice, the programmable device including an interconnect structure thatincludes a plurality of domains, each domain including at least onegroup of input lines and at least one group of routing lines, with therebeing one group of routing lines for each group of input lines and therebeing a number of sets of routing lines, the structure operable toconnect lines in each group of input lines to the routing lines in acorresponding set of routing lines, and to connect the routing lines ineach set of routing lines with the routing lines contained in other setsof routing lines within the same group, and wherein the lines of eachdomain are disjoint relative to the lines of the other domains.
 23. Theelectronic system of claim 22 wherein the programmable device comprisesan FPGA.
 24. The electronic system of claim 22 wherein the electronicsubsystem includes a computer system.
 25. A method of generatingprogramming instructions for interconnecting components within aprogrammable device, comprising: defining at least one independent groupof input lines, each group having a number of input lines; defining anequal number of groups of routing lines, each group having a number ofrouting lines; defining sets of routing lines within each group ofrouting lines; generating instructions for interconnecting each group ofinput lines to a corresponding group of routing lines; and generatinginstructions for interconnecting the routing lines in respective sets ofrouting lines within each groups to the routing lines of the other setsof routing lines within the same group.
 26. The method of claim 25wherein defining at least one independent group of input lines comprisesdefining such groups of input lines as a function of logical equivalenceof input lines within the programmable device.
 27. The method of claim25 wherein defining at least one independent group of input linescomprises defining such groups of input lines as a function of thefunctionality of input lines within the programmable device.
 28. Themethod of claim 25 wherein defining at least one independent group ofinput lines comprises defining such groups of input lines as a functionof where logic circuitry associated with each group of input lines is tobe physically located within the programmable device.
 29. The method ofclaim 25 further comprising applying the programming instructions to anFPGA.
 30. The method of claim 25 further including generatinginstructions for programming logic associated with one independent groupof input lines in a first portion of the programmable device andgenerating instructions for programming logic associated with adifferent independent group of input lines in a physically separatesecond portion of the programmable device.